[Hardware] SiFive Tapes Out First 5nm TSMC RISC-V Chip With 7.2 Gbps HBM3

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SiFive on Tuesday said that that its OpenFive division has successfully taped out the company's first system-on-chip (SoC) on TSMC's N5 process technology. The SoC can be used for AI and HPC applications and can be further customized by SiFive customers to meet their needs.

 

Meanwhile, elements from this SoC can be licensed and used for other N5 designs without any significant effort.

 

The SoC contains the SiFive E76 32-bit CPU core(s) for AI, microcontrollers, edge-computing, and other relatively simplistic applications that do not require full precision.

 

It uses OpenFive's D2D (die-to-die) interface for 2.5D packages as well as OpenFive's High Bandwidth Memory (HBM3) IP subsystem, which includes a controller and PHY that supports data transfer rates of up to 7.2 Gbps.

 

The announcement represents a milestone for SiFive and OpenFive, as the SoC is the first RISC-V-based device to be made using a 5nm node. Meanwhile, the announcement also contains two interesting facts.

 

The first one is of course OpenFive's implementation of an HBM3 solution and its rather bold data transfer rate expectation (2X compared to the fastest HBM2E available today).

 

The second one is OpenFive's D2D interface for chiplets that uses 16 Gbps NRZ signals with clock forwarding architecture, comprised of 40 IOs per channel, and provides throughput of up to ~1.75Tbps/mm. 

 

 

 

The current design will hardly ever be used 'as is', but parties interested in building a high-performance 5nm RISC-V SoC for AI or HPC applications can take it as a the base design and equip it with their own or third-party IP (e.g., custom accelerators, high-performance FP64-capable cores, etc.).

 

Alternatively, all three key components of the SoC implemented using TSMC's N5 node — the E76 core, the D2D interface and its physical implementation (which includes built-in PLL, programmable output drivers, and link training state machines), and the HBM3 memory solution (controller, I/O, PHY) — can be licensed separately.

 

The tape out means that the documentation for the chip has been submitted for manufacturing to TSMC, which essentially means that the SoC has been successfully simulated. The silicon is expected to be obtained in Q2 2021.

 

Sursa